搜索资源列表
DDC.rar
- verilog语言实现的数字下变频设计。 在ALTERA的QUARTUS ii下实现。实用,好用。,Verilog language implementation of the digital down-conversion design. ALTERA at the implementation of QUARTUS ii. Practical, easy to use.
Verilog.rar
- verilog HDL 4×4矩阵键盘驱动程序包括硬件电路图,verilog
fpga_jpeg
- 图像jpeg压缩算法,用verilog HDL在FPGA上的实现 -Jpeg image compression algorithm, using verilog HDL Implementation in FPGA
Chapter10
- 第十章的代码。 本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相
FIFO_8_8
- FIFO先进先出队列,一种缓存、或一种管道、设备、接口(Verilog HDL程序,内附说明)-FIFO FIFO queue, a cache, or a pipeline, equipment, Interface (Verilog HDL program, containing a note)
pwm
- pwm的占空比和死区时间可调的Verilog HDL程序设计和测试-duty cycle of pwm and adjustable dead time of the Verilog HDL design and testing procedures
PIPE_LINING_CPU_TEAM_24
- 采用Quatus II编译环境,使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令(均不考虑虚拟地址和Cache,并且默认为小端方式): add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,
dwt2d_latest[1].tar
- 小波变换的开源代码(Verilog HDL)包括有测试文件,本人看过,挺好。-code of dwt
mult_piped_8x8
- 8位乘8位的流水线乘法器,采用Verilog hdl编写-8 x 8-bit pipelined multiplier, used to prepare Verilog hdl
speech
- 用verilog HDL实现自相关算法! RTL级可综合代码! 通过modelsim5.6仿真和quartusii7.1综合!-Verilog HDL using auto-correlation algorithm to achieve! RTL-level code can be integrated! Through simulation and modelsim5.6 integrated quartusii7.1!
Verilog_Hdl48FIR
- verilog hdl fir 48阶-verilog hdl fir
LMS_filter
- verilog HDL 写的LMS滤波器-LMS filter using verilog HDL language
TLC549
- verilog TLC549AD采样程序 ,速度200K,在LED和数码管上显-verilog TLC549AD sampling procedures, the speed of 200K, in the LED and digital tube significantly
HDLC
- verilog HDL语言编写的HDLC协议的IP核,包括通讯控制及CRC。-written in verilog HDL HDLC protocol IP core, including communications control and CRC.
USB2.0IP(RTL)
- USB2.0 IP核,ASIC,FPGA可用,Verilog HDL源代码-USB2.0 IP,Verilog HDL
IDCT
- 用verilog HDL语言编写的IDCT程序,可以计算8*8的整形数矩阵,用ISE 9.1i编译通过-Using verilog HDL language of the IDCT program can calculate the number of 8* 8 matrix of plastic, with ISE 9.1i compiled by
alu32bit
- verilog hdl alu module it is 32bit alu and 1bit alu
X-HDL3.2.52
- vhdl和Verilog HDL相互转换的软件,很难找的一款-vhdl and Verilog HDL mutual conversion software, very difficult to find a
ds18b20
- 单路DS18B20的verilog HDL 代码,精度为1℃无须转换数据,直接输出结果。占用300个LE资源。-Single DS18B20 the verilog HDL code, and an accuracy of 1 ℃ without converting the data, direct output. Occupy 300 LE resources.
CLOCK
- 文通过ALTERA公司的quartus II软件,用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为:计时功能,24小时制计时显示;通过七段数码管动态显示时间;校时设置功能,可分别设置时、分、秒;跑表的启动、停止 、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital